1. Field of the Invention
The present invention relates to a polishing liquid used in a process of producing a semiconductor integrated circuit and a polishing method using the same. More specifically, the present invention relates to a polishing liquid that can be preferably used for the formation of a gate on a semiconductor substrate and a polishing method using the same. In particular, the present invention relates to a polishing liquid for polishing a semiconductor substrate having a layer containing polysilicon or modified polysilicon by chemical mechanical polishing and a polishing method using the same.
2. Description of the Related Art
In recent years, in the development of semiconductor devices such as a semiconductor integrated circuit (hereinafter sometimes referred to as an “LSI”), high density and high integration by miniaturization and lamination of wiring have been required in order to realize reduced size and high speed. As a technique for achieving the above, various techniques, such as chemical mechanical polishing (hereinafter sometimes referred to as “CMP”), have been used. CMP is an essential technique at the time of planarizing the surface of films to be processed such as an interlayer insulating film, plug formation, formation of embedded metal wiring, or the like, and thereby smoothing of a substrate or the like is performed.
A usual CMP process includes: adhering a polishing pad onto a circular polishing platen; immersing the surface of the polishing pad in a polishing liquid; pressing the surface (surface to be polished) of a substrate (wafer) against the pad, and rotating both the polishing platen and the substrate while a given pressure (polishing pressure) is applied thereto from the rear face to planarize the surface of the substrate by the mechanical friction generated.
In recent years, CMP has been increasingly applied to respective processes in semiconductor manufacturing. For example, CMP is applied to a gate formation process in the manufacturing of transistors.
In conventional transistors, a gate mainly containing modified polysilicon in which impurities, such as B, are doped in polysilicon, has been manufactured. However, in transistors after the 45 nm generation, the use of a gate insulating film with a high dielectric constant (High-k film) and a metal gate electrode in place of conventional polysilicon has been examined so as to achieve both reduction in power consumption during a standby state and high current driving ability. Some techniques to which these have been applied have been proposed. For example, a method has been proposed which includes: forming a dummy gate insulating film and a dummy gate electrode; doping impurities into a polycrystalline silicon film in a self-alignment manner to form a source-drain diffusion layer; removing the dummy gate insulating film and the dummy gate electrode; and then forming a gate insulating film with a high dielectric constant and a metal gate electrode (e.g., Japanese Patent Application Laid-Open (JP-A) Nos. 2006-339597, 2006-344836, and 2007-12922).
Further, some techniques for forming a metal gate electrode have been proposed. As one example thereof, there is a fully silicided gate (hereinafter referred to as a “FUSI gate”). The FUSI gate is formed by siliciding a gate electrode formed with polysilicon in the same manner as in a conventional CMOS process. Conventionally, only the upper part of a gate electrode is silicided, but in the FUSI gate, the entire gate electrode is silicided. Since the technique of the conventional CMOS process is useful in the case of the FUSI gate compared with the case of forming a metal gate electrode by a damascene process, the FUSI gate is advantageous in terms of process construction.
In recent years, it has been proposed to, in such formation of a gate using polysilicon or modified polysilicon (hereinafter sometimes collectively referred to simply as “polysilicon or the like”), selectively perform CMP with respect to the polysilicon or the like and second and third materials covering the periphery thereof (e.g., JP-A 2005-93816). However, when a body to be polished containing polysilicon or the like is polished by CMP using a known polishing liquid, there arises a problem that the polysilicon or the like which is intended to remain as a gate material is excessively polished. This problem has led to, for example, deterioration in performance of the obtained LSI.